Input protection circuitry is an essential part of modern integrated circuits, particularly in the area of field effect transistor based devices. Extremely small delicate device structures are very sensitive to high voltages. The threat of high voltage damage begins during fabrication of integrated circuits, exists during installation of integrated circuits into products and continues throughout the service life of the integrated circuits.
High voltage damage from electrostatic discharge may occur during installation of integrated circuits into products. Sources of electrostatic charge include the human body, within which charge is generated, and installation tools having residual charge. Electrostatic charge may be transferred to integrated circuits through physical contact. Subsequent to installation, high voltage damage is usually the result of a power surge. These high voltages may destroy integrated circuits, thus requiring expensive and tedious repairs on fully manufactured devices which could have been avoided by providing a mechanism for dissipation of the high voltage on the integrated circuit. This problem is particularly acute in MOS (metal oxide semiconductor) field effect transistor type integrated circuits.
Techniques presently used to build input/output structures on VLSI chips include a layout technique referred to as ladder structures. A ladder structure is formed by dividing a "wide" device into multiple parallel devices. During and ESD event, an N-channel device is susceptible to damage. This is particularly true if the source/drain of the N-channel device is formed as an LDD (lightly doped drain). The N-channel device is even more susceptible to damage if the diffusions are reacted with TiSi.sub.2. One phenomenon reported to be causing low failure thresholds is that all of the devices that are in parallel, to form the one large device, do not conduct the large current required to dissipate the power of an ESD strike. Very high power being dissipated in a small area causes "current crowding" and a very real possibility that an N-channel device will be damaged.
Therefore, it is highly desirable to provide an input protection structure that protects an integrated circuit from damage caused by electrostatic discharge events.